(1) Field of the Invention
The present invention relates to a crystal oscillation circuit and, more particularly, to a crystal oscillation circuit which is constituted by a MOS field effect transistor and which is operable in low power consumption.
(2) Description of the Related Art
FIG. 1 is a schematic circuit diagram showing an example of a conventional crystal oscillation circuit of a low power consumption type. As shown in FIG. 1, such oscillation circuit comprises a voltage regulating circuit 1, a CMOS inverter circuit 2 consisting of a P-channel MOS field effect transistor (hereinafter referred to as "PMOS-FET") 3 and an N-channel MOS field effect transistor (hereinafter referred to as "NMOS-FET") 4, a resistor 5, a crystal resonator 6, and capacitors 7 and 8. The crystal oscillation circuit of the type which is frequently and ordinarily used is formed, with respect to an output of the voltage regulating circuit 1, by such CMOS inverter circuit 2 which functions as an amplifier, a feedback circuit which includes the resistor 5 and the capacitors 7, 8, and the crystal resonator 6.
The conventional crystal oscillation circuit explained above is formed by a complementary pair of the PMOS-FET 3 and the NMOS-FET 4, however, as the gate voltage V.sub.G of the CMOS inverter circuit 2 oscillates substantially in sinusoidal waves with a result that a through-current flows in the CMOS inverter circuit 2 and thus the current consumption becomes high as shown by a voltage-current characteristic curve 101 in FIG. 2 and, moreover, the power consumption greatly increases with the rise of the power source voltage supplied to the circuit. In order to cope with this problem, conventionally, the crystal oscillation circuit in which low power consumption is required is provided with such voltage regulating circuit 1 as shown in FIG. 1, whereby the power source voltage supplied to the CMOS inverter circuit 2 is restricted so as to suppress the power consumption.
In the conventional crystal oscillation circuit of a low power consumption type explained above, in order to enable the oscillation to start, it is necessary to maintain the output voltage of the voltage regulating circuit 1 at a voltage higher than .vertline.V.sub.TP .vertline.+V.sub.TN and this is one of the reasons that the realization of a circuit with a low power consumption is being hindered. Here, the voltage V.sub.TP is a threshold voltage of the PMOS-FET 3 and the voltage V.sub.TN is a threshold voltage of the NMOS-FET 4. That the oscillation circuit does not oscillate unless the output voltage of the voltage regulating circuit 1 is maintained at or higher than .vertline.V.sub.TP .vertline.+V.sub.TN is accounted for by the reason that, since between the input and output terminals of the CMOS inverter circuit 2 is connected the feedback resistor 5, the supply voltages for the respective PMOS-FET 3 and NMOS-FET 4 become approximately half the power source voltage and, under this state, both the PMOS-FET 3 and the NMOS-FET 4 are in their OFF-states thereby preventing the start of oscillation.
A voltage-current characteristic line 102 in FIG. 2 shows the current consumption by the conventional crystal oscillation circuit of a low power consumption type. As apparent from this line 102, with the maintenance of the power supply voltage at or higher than .vertline.V.sub.TP .vertline.+V.sub.TN, the power supply current, that is, the consumption current remains at a considerably high level and, thus, it is a disadvantage that the power consumption is still large.